Cornerstone Peripherals Technology Cornerstone Professional P1500 User Manual
Browse online or download User Manual for TVs & monitors Cornerstone Peripherals Technology Cornerstone Professional P1500. 通訊多媒體核心設計 (Multimedia Communication IP Design) 課程目標
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- Table of contents
- BOOKMARKS
- 通訊多媒體核心設計 1
- (Multimedia Communication IP 1
- Grading & Textbook 2
- Term Project 3
- (Design Service) 5
- After 2000 5
- Accelerating Technology and 6
- Moore’s Law: Driving Advances 6
- Silicon Process Roadmaps 7
- System Revolution 8
- Technology Convergence 9
- It’s a convergence world ! 9
- What does SOC contains 10
- Interface 10
- Consumer 10
- SOC Technology Improvement 10
- Grow to 4.4 B in 2000 11
- Reach 11.4 B in 2003 11
- The Design Productivity Gap 12
- (includes 13
- SOC Example: 14
- Bluetooth Block Schematic 14
- Bluetooth SOC Microphotograph 14
- Motion Engine in PS2 15
- Transceiver IC Block Diagram 15
- Chip Photograph 16
- SOC Application Product 16
- RMM2 - Table of Contents 17
- Programmable processor 19
- On-chip memory 19
- Peripheral interfaces 19
- Embedded software 19
- Need integration --> O 20
- SOC Design Challenge 21
- A Quadruple Challenges in SOC 22
- Design Challenges - Silicon 22
- Complexity 22
- Design Challenge - System 23
- Heterogeneity 23
- Design Challenge - DSM Effect 23
- Problems in SOC Era 24
- Overview of SOC 25
- What is IP ? 25
- Soft IP (“Code”) 26
- Hard IP (“physical”) 27
- IP value 28
- IP sources 28
- From previous IP 28
- From IP vendors 28
- Issues in IP Integration 29
- System-level IC Development 30
- Key to Success 30
- Conventional framework 32
- New framework 32
- For system/design houses 32
- For ASIC vendors 32
- Your SOC Design Foundry 33
- Textbook 34
- Digital IP Authoring 35
- RTL Coding Guideline 35
- SOC and IP Core Design 35
- Waterfall Model 36
- System Design Flow - SOC 37
- Spiral Model 37
- Top-Down and Bottom-Up 38
- Bottom-up fashion 38
- Fundamental Elements of IP 38
- Specification Requirements 39
- Types of Specification (1/2) 39
- Executable specification 40
- System Design Process 41
- Define the target spec 41
- Sub-module design 41
- Top Level Macro Design Flow 42
- Need to create a 42
- Test the behavior mode 42
- Partition the design into 42
- Sub-Block Design Flow 42
- Preparing macro for 44
- SoC integration 44
- Macro Productization 45
- Design for Reuse IP 45
- MPY-generator 45
- fit in multiple technology 45
- Why to parameterize IP ? 46
- Parameterizable types 46
- Why Coding Guideline ? 47
- Contents 49
- Coding Practices 51
- Portability 51
- secret=6’h 591003; //??? 51
- GTECH or DesignWare 51
- Clocks and Resets 52
- Synchronicity 52
- Sequential Blocks 53
- Combinational Blocks 53
- Verilog-Mode 54
- Module Tedium? 54
- Less time typing 55
- What would we like in a fix? 56
- Idea… Use comments! 56
- Sensitivity Lists 57
- Argument Lists 57
- Automatic Wires 58
- Automatic Registers 58
- Simple Instantiations 59
- State Machines 59
- Making upper level modules 60
- Verifiable RTL 60
- Verifiable RTL (cont.) 61
- Coding for Synthesis 61
- If-then-else 61
- Coding for Synthesis (cont.) 62
- Coding for FSM 62
- Coding for DfT 63
- Partitioning 63
- Partitioning (cont.) 64
- SoC Integration Process 65
- ex: floor plan 65
- IP Selection 66
- Integration Problems 66
- VC Interface 68
- AMBA, VCI, OCP, PCI 68
- Concept of Virtual Socket 68
- AMBA 2.0 specifies 69
- ARM OCB-AMBA 70
- Advanced VCI (AVCI) 70
- Basic VCI (BVCI) 70
- Peripheral VCI (PVCI) 70
- VCI usage with a bus 71
- VCI bus hierarchy 71
- Clock distribution 72
- Power and ground 72
- Test structure 72
- Integrating Memory 73
- Functional Models 74
- Behavioral Models 74
- Behavioral and ISA Models 75
- Bus Functional Model 75
- Full Functional Model 76
- Synthesis Timing Model 76
- System Integration Guidelines 77
- Clocking 78
- Clocking (cont.) 79
- Tri-state bus 80
- Reduce supply voltage 81
- Reduce switching activity 81
- Clock gating 82
- Two alternatives 84
- buffering the bus clock 85
- Tri-state bus is not good 86
- Design for Test 87
- System-level test 87
- Design for Test (cont.) 87
- SoC Verification 89
- HW/SW co-simulation 90
- System integration 90
- Reuse-based SoC Design 91
- In-house development 91
- Employee training 92
- Tool flow 92
- VCX (cont.) 93
- VCX Homepage 94
- IP Catalyst Programs 95
- Some References 96
- Conclusions 96
- Platform-Based SOC Design 97
- Platform-Based SOC 97
- From IP to Platform 98
- 2000 -> 50 % 98
- 2005 -> 80% 98
- 2010 -> 95% 98
- Benefits for Platform Based 98
- What is Platform-Based Design 99
- Prototype vs. Platform 99
- How to Works? 100
- Platform-Based Integration 100
- How to Build a Platform 101
- Ingredients of Platform 101
- Platform-Based Design 102
- Design Stage - Architecture 103
- Evaluation 103
- Verification 104
- Type of Platform 105
- Platform design 105
Summary of Contents
1通訊多媒體核心設計(Multimedia Communication IP Design)蔡宗漢(Tsung-Han Tsai)Dept. of E.E., N.C.U.NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai2課程目標
10NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai19What does SOC containsDSPNetworkEncryption, FECMixedBus InterfaceConsumerCPU/MCUPeripher
100NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai199How to Works?NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai200Platform-Bas
101NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai201Ingredients of PlatformNCUEE -- Multimedia Communication IP DesignTsung-Han Tsai202Ho
102NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai203Platform-Based DesignNCUEE -- Multimedia Communication IP DesignTsung-Han Tsai204Desi
103NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai205Design Stage - Design PartitionNCUEE -- Multimedia Communication IP DesignTsung-Han T
104NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai207Design Stage - Integration & VerificationNCUEE -- Multimedia Communication IP Des
105NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai209Type of PlatformNCUEE -- Multimedia Communication IP DesignTsung-Han Tsai210Platform
11NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai21SOC Market Potential Grow to 4.4 B in 2000 Primary market in cost reduction segment P
12NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai23The Design Productivity GapNCUEE -- Multimedia Communication IP DesignTsung-Han Tsai24C
13NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai25VLSI Design TrendsNCUEE -- Multimedia Communication IP DesignTsung-Han Tsai26Handset si
14NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai27SOC Example: Bluetooth Block SchematicNCUEE -- Multimedia Communication IP DesignTsung-
15NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai29SOC Example:Motion Engine in PS2NCUEE -- Multimedia Communication IP DesignTsung-Han Ts
16NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai31Chip PhotographNCUEE -- Multimedia Communication IP DesignTsung-Han Tsai32SOC Applicati
17NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai33RMM2 Reuse Methodology Manual For System-on-a-Chip Designs, 2nd Edition by Michael Kea
18NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai35SOC Definition “RMM” defines a SOC design should consists of: A microprocessor and its
19NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai37Surviving the SOC Revolution -Table of Contents1. Moving to System-on-Chip Design. 2. Ov
2NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai3內容綱要 Introduction to IP and SoC IP Core Design Flow Algorithm and Architecture Ex
20NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai39SOC Definition - generally heard SOC = CPU + embedded memory + I/O SOC = DSP + memory
21NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai41Overview of SOC Technology Trend in Microelectronics SOC Design StrategySOC Design C
22NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai43A Quadruple Challenges in SOCNCUEE -- Multimedia Communication IP DesignTsung-Han Tsai4
23NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai45Design Challenge - System Heterogeneity Embedded software as a key design problem SOC
24NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai47SOC - Revolution or Evolution ? EDA and ASIC vendors said that SOC is a revolution of I
25NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai49Overview of SOC Technology Trend in Microelectronics SOC Design Strategy SOC Design
26NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai51Type of IP Soft IP (“Code”) Synthesizable HDL description at RTL level Flexible: can
27NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai53Type of IP (cont.) Hard IP (“physical”) Provide as a blackbox (GDSII) Usually very ti
28NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai55IP value Foundation IP Cell MegaCell Star IP ARM processors Niche IP ARM (low pow
29NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai57Sampling of Cores Classified byFunctionalityNCUEE -- Multimedia Communication IP Design
3NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai5Term Project Discuss and implement one of the related design discussed in our lecture. T
30NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai59System-level IC DevelopmentNCUEE -- Multimedia Communication IP DesignTsung-Han Tsai60K
31NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai61Design for Use To be reusable, be usable first ! Documentation Code quality Through
32NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai63Role Change in SOC Era Conventional framework System/design houses take responsibility
33NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai65To Be Reusable or Not to Be Normally designer teams treat design reuse as a burden beca
34NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai67References Shin-Wu Tung, “Reuse Methodology Manual for SoC Designs”. Juinn-Dar Huang,
35NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai69Agenda Overview of SOC Reuse Methodology Manual (RMM) for SOCDigital IP AuthoringRTL
36NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai71System Design Flow - Conventional High stage performance goal must be met for the low s
37NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai73System Design Flow - SOC Parallel, concurrent development of hardware and software. Pa
38NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai75Top-Down and Bottom-Up Traditional top-down design flow Recursively partition the desi
39NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai77Specification Requirements Functionality Performance/area/power Test Coverage (fault
4NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai7Agenda Overview of SOC Reuse Methodology Manual (RMM) for SOC Digital IP Authoring RT
40NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai79Types of Specification (2/2) Executable specification Usually written in C/C++, SDL, V
41NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai81System Design ProcessNCUEE -- Multimedia Communication IP DesignTsung-Han Tsai824 Major
42NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai83Top Level Macro Design FlowSTEP 1 Specification Need to create a behavior model and te
43NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai85Sub-Block Design FlowSTEP 3NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai86S
44NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai87Sub-Block Integration FlowSTEP 5 Tasks Generate top-level HDL and netlist Perform fun
45NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai89Macro ProductizationNCUEE -- Multimedia Communication IP DesignTsung-Han Tsai90Design f
46NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai91Parameterized IP design Why to parameterize IP ? Provide flexibility in interface and
47NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai93Outline SoC Design Methodology RTL Coding Guidelines SoC Integration Design Verifica
48NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai95Principles Readability Simplicity Locality Portability Reusability Reconfigurabili
49NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai97File Header Should be included for all source files Contents author information revi
5NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai9cefdgExample: Telecommunications ICSemiconductor Industry De-integrationUMC, JapanUMC, Tai
50NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai99Comments and Formats Appropriate comments process (always block), function,… Comment
51NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai101Coding Practices Little-endian for multi-bit bus [31:0] instead [0:31] Operand sizes
52NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai103Clocks and Resets Simple clocking is easier to understand, analyze, and maintain Avoi
53NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai105Combinational Blocks Combinational block use blocking assignments minimize signals r
54NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai107Verilog-ModeNCUEE -- Multimedia Communication IP DesignTsung-Han Tsai108Module Tedium?
55NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai109Why is this information redundant? The argument list is a duplication of the input/out
56NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai111 Don’t want a new language All tools would need a upgrade! (Verilog 2000 unfortunate
57NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai113Sensitivity ListsNCUEE -- Multimedia Communication IP DesignTsung-Han Tsai114Argument
58NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai115Automatic WiresNCUEE -- Multimedia Communication IP DesignTsung-Han Tsai116Automatic R
59NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai117Simple InstantiationsNCUEE -- Multimedia Communication IP DesignTsung-Han Tsai118State
6NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai11Accelerating Technology and ComplexityNCUEE -- Multimedia Communication IP DesignTsung-H
60NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai119Making upper level modules Building null or shell modules You want a module with same
61NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai121Verifiable RTL (cont.)NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai122Codi
62NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai123Coding for Synthesis (cont.)conditional assignment infers a mux with slower simulatio
63NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai125Coding for DfT Avoid tri-state buses bus contention, bus floating using MUX will be
64NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai127Partitioning (cont.) Avoid timing exception point-to-point, false path, multi-cycle p
65NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai129Outline SoC Design Methodology RTL Coding Guidelines SoC Integration Design Verific
66NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai131IP Selection Good documentation Documents, scripts, ….. Comprehensive verification e
67NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai133Integrated IP Example (IP Provider)• The IP provider then uses VERA CORE to turn the VE
68NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai135VC Interface An universal bus standard is the ultimate goal Different power, performa
69NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai137Interface designs Provide communication link with other IPs Too simplified interface
7NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai13Silicon Process RoadmapsNCUEE -- Multimedia Communication IP DesignTsung-Han Tsai14Techn
70NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai139ARM OCB-AMBA A typical AMBA systemNCUEE -- Multimedia Communication IP DesignTsung-Ha
71NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai141VCI usage with a bus Used as an interface to a wrapper1. OCB suppliers provide VCI wra
72NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai143VCI (OCB) bus hierarchy Multiple buses within a system Organized by bandwidthNCUEE -
73NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai145Integrating Memory Memory block is usually obtained from the memory compilersSynchron
74NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai147Functional Models Functional models of different abstractions Tradeoffs between accur
75NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai149Behavioral and ISA ModelsNCUEE -- Multimedia Communication IP DesignTsung-Han Tsai150B
76NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai151Full Functional ModelNCUEE -- Multimedia Communication IP DesignTsung-Han Tsai152Synth
77NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai153System Integration Guidelines System-level guidelines For producing well-designed IPs
78NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai155Synchronous vs. Asynchronous Avoid asynchronous and multi-cycle paths Register-based
79NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai157Clocking (cont.) Rule- Number of clock domains and clock frequencies must be document
8NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai15Low Cost A transistor cost $30 in 1960 8080 (5,000 tx) cost $150 in 1974 3 cents/tx P
80NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai159Reset (cont.) Rule The basic reset strategy for the chip must be documented. It is pa
81NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai161System Interconnection (2/2) Multiplexer is better than Tri-state buffer for SoC desig
82NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai163Low Power Issue for Memories Memory Low-power memory design Memory = address decode
83NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai165Low Power Issue for Memories (cont.) Trade fault converge for power consumptionNCUEE
84NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai167Subblock InterfaceSubblock 1 Subblock 2Macro A•Registering the output of subblock is su
85NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai169On-Chip Bus (OCB) (cont.) A lower-speed bus is used to connect all of the modules To
86NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai171Clock Distribution•Rule-The design team must decide on the basic clock distribution arc
87NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai173Design for TestSystem-level testplan must be developed in the initial design stage Te
88NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai175Design For Timing Closure : Physical Design IssueThe key to achieving rapid timing clos
89NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai177SoC Verification Verification takes 60% - 80% of the design time Key to success Qual
9NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai17Digital RevolutionTechnology Convergence -It’s a convergence world !Mainframe/Minicompute
90NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai179Deliverables for Soft Macros Product files Synthesizable RTL Application notes All
91NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai181Outline SoC Design Methodology RTL Coding Guidelines SoC Integration Design Verific
92NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai183Key Steps Develop the reuse methodology Employee training Tool flow Demonstrate the
93NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai185VCX (Virtual Component Exchange) The VCX, an industry-backed initiative, is dedicated
94NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai187VCX HomepageNCUEE -- Multimedia Communication IP DesignTsung-Han Tsai188Virtual Socket
95NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai189OpenMORE Open Measure of Reuse Excellence (OpenMORE) Based on Reuse Methodology Manua
96NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai191Some References Books and Reports− “Reuse Methodology Manual for System-On-A-Chip Desi
97NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai193Platform-Based SOC Design Embedded Processor for SOC Embedded DSP for SOC SOPC - FP
98NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai195From IP to Platform SOC design increasingly based on pre-designed components (IP reuse
99NCUEE -- Multimedia Communication IP DesignTsung-Han Tsai197What is Platform-Based Design A Pre-designed and Pre-verified application architecture
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